module ringcounter_tb;

reg          clk;
reg          rstn;
reg          en_i;
wire  [3:0]  cnt_o;
wire         q0_o;
wire         q1_o;
wire         q2_o;
wire         q3_o;

initial
begin
    clk  = 0;

    rstn = 1;
    #50    rstn = 0;
    #100   rstn = 1;

    en_i = 1;

    #800 $finish;
end

always #20 clk = ~clk;

initial begin
  $dumpfile("build/dump.vcd");
  $dumpvars;
end

ringcouter u_ringcounter(
                         .cnt_o(cnt_o),
                         .q0_o(q0_o),
                         .q1_o(q1_o),
                         .q2_o(q2_o),
                         .q3_o(q3_o),
                         .clk(clk),
                         .rstn(rstn),
                         .en_i(en_i)
                         );

endmodule
